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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 5 m s 8-bit adc with track/hold ad7575 functional block diagram track and hold clock oscillator dac sar comp control logic latch and three state output drivers ad7575 v dd ain agnd v ref clk cs rd tp busy dgnd db7 db0 general description the ad7575 is a high speed 8-bit adc with a built-in track/ hold function. the successive approximation conversion tech- nique is used to achieve a fast conversion time of 5 m s, while the built-in track/hold allows full-scale signals up to 50 khz (386 mv/ m s slew rate) to be digitized. the ad7575 requires only a single +5 v supply and a low cost, 1.23 v bandgap reference in order to co nvert an input signal range of 0 to 2 v ref . the ad7575 is designed for easy interfacing to all popular 8-bit microprocessors using standard microprocessor control signals ( cs and rd ) to control starting of the conversion and reading of the data. the interface logic allows the ad7575 to be easily configured as a memory mapped device, and the part can be interfaced as slow-memory or rom. all data outputs of the ad7575 are latched and three-state buffered to allow direct connection to a microprocessor data bus or i/o port. the ad7575 is fabricated in an advanced, all ion-implanted high speed linear compatible cmos (lc 2 mos) process and is available in a small, 0.3" wide, 18-lead dip, 18-lead soic or in other 20-terminal surface mount packages. features fast conversion time: 5 m s on-chip track/hold low total unadjusted error: 1 lsb full power signal bandwidth: 50 khz single +5 v supply 100 ns data access time low power (15 mw typ) low cost standard 18-lead dlps or 20-terminal surface mount packages product highlights 1. fast conversion time/low power the fast, 5 m s, conversion time of the ad7575 makes it suitable for digitizing wideband signals at audio and ultra- sonic frequencies while retaining the advantage of low cmos power consumption. 2. on-chip track/hold the on-chip track/hold function is completely self-contained and requires no external hold capacitor. signals with slew rates up to 386 mv/ m s (e.g., 2.46 v peak-to-peak 50 khz sine waves) can be digitized with full accuracy. 3. low total unadjusted error the zero, full-scale and linearity errors of the ad7575 are so low that the total unadjusted error at any point on the trans- fer function is less than 1 lsb, and offset and gain adjust- ments are not required. 4. single supply operation operation from a single +5 v supply with a low cost +1.23 v bandgap reference allows the ad7575 to be used in 5 v microprocessor systems without any additional power supplies. 5. fast digital interface fast interface timing allows the ad7575 to interface easily to the fast versions of most popular microprocessors such as the z80h, 8085a-2, 6502b, 68b09 and the dsp processor, the tms32010. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
rev. b C2C ad7575Cspecifications (v dd = +5 v, v ref = +1.23 v, agnd = dgnd = 0 v; f clk = 4 mhz external; all specifications t min to t max unless otherwise noted) parameter j, a versions 1 k, b versions s version t version units conditions/comments accuracy resolution 8 8 8 8 bits total unadjusted error 2 1 2 1 lsb max relative accuracy 1 1/2 1 1/2 lsb max minimum resolution for which no missing codes is guaranteed 8 8 8 8 bits max full-scale error +25 c 1 1 1 1 lsb max full-scale tc is typically 5 ppm/ c t min to t max 1 1 1 1 lsb max offset error 2 +25 c 1/2 1/2 1/2 1/2 lsb max offset tc is typically 5 ppm/ c t min to t max 1/2 1/2 1/2 1/2 lsb max analog input voltage range 0 to 2 v ref 0 to 2 v ref 0 to 2 v ref 0 to 2 v ref volts 1 lsb = 2 v ref /256; see figure 16 dc input impedance 10 10 10 10 m w min slew rate, tracking 0.386 0.386 0.386 0.386 v/ m s max snr 3 45 45 45 45 db min v in = 2.46 v p-p @ 10 khz; see figure 11 reference input v ref (for specified performance) 1.23 1.23 1.23 1.23 volts 5% i ref 500 500 500 500 m a max logic inputs cs , rd v inl , input low voltage 0.8 0.8 0.8 0.8 v max v inh , input high voltage 2.4 2.4 2.4 2.4 v min i in , input current +25 c 1 1 1 1 m a max v in = 0 or v dd t min to t max 10 10 10 10 m a max v in = 0 or v dd c in , input capacitance 3 10 10 10 10 pf max clk v lnl , input low voltage 0.8 0.8 0.8 0.8 v max v inh , input high voltage 2.4 2.4 2.4 2.4 v min i inl , input low current 700 700 800 800 m a max v inl = 0 v i inh , input high current 700 700 800 800 m a max v inh = v dd logic outputs busy , db0 to db7 v ol , output low voltage 0.4 0.4 0.4 0.4 v max i sink = 1.6 ma v oh , output high voltage 4.0 4.0 4.0 4.0 v min i source = 40 m a db0 to db7 floating state leakage current 1 1 10 10 m a max v out = 0 to v dd floating state output capacitance 3 10 10 10 10 pf max conversion time 4 with external clock 5 5 5 5 m sf clk = 4 mhz with internal clock, t a = +25 c5 5 5 5 m s min using recommended clock 15 15 15 15 m s max components shown in figure 15 power requirements 5 v dd +5 +5 +5 +5 volts 5% for specified performance i dd 6 6 7 7 ma max typically 3 ma with v dd = +5 v power dissipation 15 15 15 15 mw typ power supply rejection 1/4 1/4 1/4 1/4 lsb max 4.75 v v dd 5.25 v notes 1 temperature ranges are as follows: j, k versions; 0 c to +70 c a, b versions; C25 c to +85 c s, t versions; C55 c to +125 c 2 offset error is measured with respect to an ideal first code transition that occurs at 1/2 lsb. 3 sample tested at +25 c to ensure compliance. 4 accuracy may degrade at conversion times other than those specified. 5 power supply current is measured when ad7575 is inactive i.e., when cs = rd = busy = logic high. specifications subject to change without notice.
ad7575 C3C rev. b timing specifications 1 limit at +25 8 c limit at t min , t max limit at t min , t max parameter (all versions) (j, k, a, b versions) (s, t versions) units conditions/comments t 1 0 0 0 ns min cs to rd setup time t 2 100 100 120 ns max rd to busy propagation delay t 3 2 100 100 120 ns max data access time after rd t 4 100 100 120 ns min rd pulse width t 5 0 0 0 ns min cs to rd hold time t 6 2 80 80 100 ns max data access time after busy t 7 3 10 10 10 ns min data hold time 80 80 100 ns max t 8 0 0 0 ns min busy to cs delay notes 1 timing specifications are sample tested at +25 c to ensure compliance. all input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 t 3 and t 6 are measured with the load circuits of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 3 t 7 is defined as the time required for the data lines to change 0.5 v when loaded with the circuits of figure 2. specifications subject to change without notice. (v dd = +5 v, v ref = +1.23 v, agnd = dgnd = 0 v) test circuits absolute maximum ratings* v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd digital input voltage to dgnd . . . . . . . C0.3 v, v dd + 0.3 v digital output voltage to dgnd . . . . . . C0.3 v, v dd + 0.3 v clk input voltage to dgnd . . . . . . . . . C0.3 v, v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd ain to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd operating temperature range commercial (j, k versions) . . . . . . . . . . . . . . 0 c to +70 c industrial (a, b versions) . . . . . . . . . . . . . C25 c to +85 c extended (s, t versions) . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . . 6 mw/ c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7575 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. b high-z to v ol a. high-z to v oh figure 1. load circuits for data access time test figure 2. load circuits for data hold time test a. v oh to high-z b. v ol to high-z warning! esd sensitive device dgnd 3k v 100pf dbn dgnd 3k v 100pf dbn +5v dgnd 3k v 10pf dbn dgnd 3k v 10pf dbn +5v
ad7575 C4C rev. b terminology least significant bit (lsb) an adc with 8-bits resolution can resolve 1 part in 2 8 (i.e., 256) of full scale. for the ad7575 with +2.46 v full-scale one lsb is 9.61 mv. total unadjusted error this is a comprehensive specification that includes full-scale error, relative accuracy and offset error. relative accuracy relative accuracy is the deviation of the adcs actual code transition points from a straight line drawn between the devices measured first lsb transition point and the measured full-scale transition point. snr signal-to-noise ratio (snr) is the ratio of the desired signal to the noise produced in the sampled and digitized analog signal. snr is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical snr for a sine wave input is given by snr = (6.02 n + 1.76) db where n is the number of bits in the adc. full-scale error (gain error) the gain of a unipolar adc is defined as the difference between the analog input levels required to produce the first and the last digital output code transitions. gain error is a measure of the deviation of the actual span from the ideal span of fs C 2 lsbs. analog input range with v ref = +1.23 v, the maximum analog input voltage range is 0 v to +2.46 v. the output data in lsbs is related to the analog input voltage by the integer value of the following expression: data (lsbs) = 256 ain 2 v ref + 0.5 slew rate slew rate is the maximum allowable rate of change of input signal such that the digital sample values are not in error. slew rate limitations may restrict the analog signal bandwidth for full-scale analog signals below the bandwidth allowed from sampling theorem considerations. ordering guide relative temperature accuracy package model 1 range (lsb) options 2 ad7575jr 0 c to +70 c 1 max r-18 ad7575jn 0 c to +70 c 1 max n-18 ad7575kn 0 c to +70 c 1/2 max n-18 ad7575jp 0 c to +70 c 1 max p-20a ad7575kp 0 c to +70 c 1/2 max p-20a ad7575aq C25 c to +85 c 1 max q-18 ad7575bq C25 c to +85 c 1/2 max q-18 ad7575sq C55 c to +125 c 1 max q-18 ad7575tq C55 c to +125 c 1/2 max q-18 ad7575se C55 c to +125 c 1 max e-20a ad7575te C55 c to +125 c 1/2 max e-20a notes 1 to order mil-std-883, class b process parts, add /883b to part number. contact local sales office for military data sheet. for u.s. standard military drawing (smd), see desc drawing #5962-87762. 2 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip, r = soic. pin configurations plcc dip/soic lccc top view (not to scale) 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 ad7575 dgnd db5 cs rd tp busy db6 db7 (msb) clk db4 db3 v dd v ref ain agnd db2 db1 db0 (lsb) top view (not to scale) 20 19 1 2 3 18 14 15 16 17 4 5 6 7 8 9 10111213 nc = no connect busy clk db7 (msb) db6 db5 ain agnd db0 (lsb) db1 db2 tp rd cs v dd v ref dgnd nc nc db4 db3 ad7575 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier nc = no connect tp busy clk db7 (msb) db6 ain agnd db0 (lsb) db1 db2 ad7575 rd cs nc v dd v ref db5 dgnd nc db4 db3
ad7575 C5C rev. b timing and control of the ad7575 the two logic inputs on the ad7575, cs and rd , control both the starting of conversion and the reading of data from the part. a conversion is initiated by bringing both of these control inputs low. two interface options then exist for reading the output data from the ad7575. these are the slow memory interface and rom interface, their operation is outlined below. it should be noted that the tp pin of the ad7575 must be hard-wired high to ensure correct operation of the part. this pin is used in testing the device and should not be used as a feedthr ough pin in double-sided printed circuit boards. slow memory interface the first interface option is intended for use with microproces- sors that can be forced into a wait state for at least 5 m s. the microprocessor (such as the 8085a) starts a conversion and is halted until the result of the conversion is read from the con- verter. conversion is initiated by executing a memory read to the ad7575 address, bringing cs and rd low. busy subse- quently goes low (forcing the microprocessor ready input low), placing the processor into a wait state. the input signal, which had been tracked by the analog input, is held on the third falling clock edge of the input clock after cs and rd have gone low (see figure 12). the ad7575 then performs a conversion on this acquired input signal value. when the con- version is complete ( busy goes high), the processor com- pletes the memory read and acquires the newly converted data. the timing diagram for this interface is shown in figure 3. address decode address latch ad7575* tp cs rd busy db0Cdb7 address bus data bus +5v a8Ca15 s0 ale ad0Cad7 ready 8085aC2 *linear circuitry omitted for clarity so = 0 for read cycles figure 4. ad7575 to 8085a-2 slow memory interface the major advantage of this interface is that it allows the micro- processor to start conversion, wait, and then read data with a single read instruction. the fast conversion time of the ad7575 ensures that the microprocessor is not placed in a wait state for an excessive amount of time. faster versions of many processors, including the 8085a-2, test the condition of the ready input very soon after the start of an instruction cycle. therefore, busy of the ad7575 must go low very early in the cycle for the ready input to be effec- tive in forcing the processor into a wait state. when using the 8085a-2, the processor s0 status signal provides the earliest possible indication that a read operation is about to occur. hence, s0 (which is low for a read cycle) provides the read signal to the ad7575. the connection diagram for the ad7575 to 8085a-2 slow memory interface is shown in figure 4. rom interface the alternative interface option on the ad7575 avoids placing the microprocessor into a wait state. in this interface, a con- version is started with the first read instruction, and the sec- ond read instruction accesses the data and starts a second conversion. the timing diagram for this interface is shown in figure 5. it is possible to avoid starting another conversion on the second read (see below). conversion is initiated by executing a memory read instruc- tion to the ad7575 address, causing cs and rd to go low. data is also obtained from the ad7575 during this instruction. this is old data and may be disregarded if not required. busy goes low, indicating that conversion is in progress, and re- turns high when conversion is complete. once again, the input signal is held on the third falling edge of the input clock after cs and rd have gone low. the busy line may be used to generate an interrupt to the microprocessor or monitored to indicate that conversion is complete. the processor then reads the newly-converted data. alternatively, the delay between the convert start (first read instruction) and the data read (second read instruction) must be at least as great as the ad7575 conversion time. for the ad7575 to operate correctly in the rom interface mode, cs and rd should not go low before busy returns high. normally, the second read instruction starts another conver- sion as well as accessing the output data. however, if cs and rd are brought low within one external clock period of busy going high, a second conversion does not occur. t 5 t 1 t 2 t 6 t 7 t conv high impedance bus new data old data high impedance bus cs rd busy data t 3 figure 3. slow memory interface timing diagram
ad7575 C6C rev. b ad7575* tp cs rd db0Cdb7 address bus data bus +5v *linear circuitry omitted for clarity address decode en a0Ca15 r/ w f 2 or e d0Cd7 6502/6809 figure 6. ad7575 to 6502/6809 rom interface ad7575* tp cs rd address bus data bus +5v *linear circuitry omitted for clarity address decode en mreq zC80 rd db7 db0 db7 db0 figure 7. ad7575 to z-80 rom interface ad7575* tp cs rd address bus data bus +5v *linear circuitry omitted for clarity address decode en men tms32010 den d7 d0 db7 db0 pa2 pa0 figure 8. ad7575 to tms32010 rom interface figures 6 and 7 show connection diagrams for interfacing the ad7575 in the rom interface mode. figure 6 shows the ad7575 interface to the 6502/6809 microprocessors while the connection diagram for interfacing to the z-80 is shown in figure 7. as a result of its very fast interface timing, the ad7575 can also be interfaced to the dsp processor, the tms32010. the ad7575 will (within specifications) interface to the tms32010, running at up to 18 mhz, but will typically work over the full clock frequency range of the tms32010. figure 8 shows the connection diagram for this interface. the ad7575 is mapped at a port address. conversion is initiated using an in a, pa instruction where pa is the decoded port address for the ad7575. the conversion result is obtained from the part using a second in a, pa instruction, and the resultant data is placed in the tms32010 accumulator. in many applications it is important that the signal sampling occurs at exactly equal intervals to minimize errors due to sam- pling uncertainty or jitter. the interfaces outlined previously require that for sampling at equidistant intervals, the user must count clock cycles or match software delays. this is especially difficult in interrupt-driven systems where uncertainty in inter- rupt servicing delays would require that the ad7575 have prior- ity interrupt status and even then redundant software delays may be necessary to equalize loop delays. this problem can be overcome by using a real time clock to control the starting of conversion. this can be derived from the clock source used to drive the ad7575 clk pin. since the sampling instant occurs three clock cycles after cs and rd go low, the input signal sampling intervals are equidistant. the resultant data is placed in a fifo latch that can be accessed by the microprocessor at its own rate whenever it requires the data. this ensures that data is not read from the ad7575 during a conversion. if a data read is performed during a conversion, valid data from the previous conversion will be accessed, but the conversion in progress may be interfered with and an incorrect result is likely. if cs and rd go low within 20 ns of a falling clock edge, the ad7575 may or may not see that falling edge as the first of the three falling clock edges to the sampling instant. in this case, the sampling instant could vary by one clock period. if it is impor- tant to know the exact sampling instant, cs and rd should not go low within 20 ns of a falling clock edge. high impedance bus new data high impedance bus high impedance bus old data data busy rd cs t 1 t 2 t 3 t 5 t 7 t 8 t 4 t 7 t 3 figure 5. rom interface timing diagram
ad7575 C7C rev. b a sampled-data input the ad7575 makes use of a sampled-data comparator. the equivalent input circuit is shown in figure 9. when a conversion starts, switch s1 is closed, and the equivalent input capacitance is charged to v in . with a switch resistance of typically 500 w and an input capacitance of typically 2 pf, the input time constant is 1 ns. thus c in becomes charged to within 1/4 lsb in 6.9 time constants or about 7 ns. since the ad7575 requires two input clock cycles (at a clock frequency of 4 mhz) before going into the compare mode, there is ample time for the input voltage to settle before the first comparator decision is made. increasing the source resistance increases the settling time re- quired. input bypass capacitors placed directly at the analog input act to average the input charging currents. the average current flowing through any source impedance can cause full-scale errors. 2pf v in c s 0.5pf s1 r on 500 v figure 9. equivalent input circuit reference input the reference input impedance on the ad7575 is code depen- dent and varies by a ratio of approximately 3-to-1 over the digi- tal code range. the typical resistance range is from 6 k w to 18 k w . as a result of the code dependent input impedance, the v ref input must be driven from a low impedance source. figure 10 shows how an ad589 can be configured to produce a nominal reference voltage of +1.23 v. 47 m f 0.1 m f + C ad589 3.3k v +5v 1.23v figure 10. reference circuit track-and-hold the on-chip track-and-hold on the ad7575 means that input signals with slew rates up to 386 mv/ m s can be converted with- out error. this corresponds to an input signal bandwidth of 50 khz for a 2.46 v peak-to-peak sine wave. figure 11 shows a typical plot of signal-to-noise ratio versus input frequency over the input bandwidth of the ad7575. the snr figures are gen- erated us ing a 200 khz sampling frequency, and the reconstructed sine w ave passes through a filter with a cutoff frequency of 50 khz. the improvement in the snr figures seen at the higher frequen- cies is due to the sharp cutoff of the filter (50 khz, 8th order chebyshev) used in the test circuit. input frequency C hz 40 100 100k snr C db 10k 1k 42 44 46 48 50 52 54 t a = +25 8 c figure 11. snr vs. input frequency the input signal is held on the third falling edge of the input clock after cs and rd go low. this is indicated in figure 12 for the slow memory interface. between conversions, the input signal is tracked by the ad7575 track-and-hold. since the sampled signal is held on a small, on-chip capacitor, it is advis- able that the data bus be kept as quiet as possible during a conversion. external clock busy rd cs input signal held here figure 12a. track-and-hold (slow memory interface) with external clock input signal held here internal clock busy rd cs figure 12b. track-and-hold (slow memory interface) with internal clock
ad7575 C8C rev. b internal/external clock the ad7575 can be used with its own internal clock or with an externally applied clock. in either case, the clock signal appear- ing at the clk pin is divided internally by two to provide an internal clock signal for the ad7575. a single conversion lasts for 20 input clock cycles (10 internal clock cycles). internal clock clock pulses are generated by the action of the external capaci- tor (c clk ) charging through an external resistor (r clk ) and discharging through an internal switch. when a conversion is complete, the internal clock stops operating. in addition to conversion, the internal clock also controls the automatic inter- nal reset of the sar. this reset occurs at the start of each con- version cycle during the first internal clock pulse. nominal conversion times versus temperature for the recom- mended r clk and c clk combination are shown in figure 13. ambient temperature C 8 c 14 7 C55 +125 C25 conversion time C m s 0 +25 +50 +75 +100 13 11 10 9 8 12 r clk = 100k v c clk = 100pf figure 13. typical conversion times vs. temperature using internal clock the internal clock is useful because it provides a convenient clock source for the ad7575. due to process variations, the actual operating frequency for this r clk /c clk combination can vary from device to device by up to 50%. for this reason it is recommended that an external clock be used in the following situations: 1. applications requiring a conversion time that is within 50% of 5 m s, the minimum conversion time for specified accuracy. a clock frequency of 4 mhz at the clk pin gives a conversion time of 5 m s. 2. applications where time related software constraints cannot accommodate time differences that may occur due to unit to unit clock frequency variations or temperature. external clock the clk input of the ad7575 may be driven directly from 74 hc, 4000b series buffers (such as 4049) or from ls ttl with a 5.6 k w pull-up resistor. when conversion is complete, the internal clock is disabled even if the external clock is still ap- plied. this means that the external clock can continue to run between conversions without being disabled. the mark/space ratio of the external clock can vary from 70/30 to 30/70. the ad7575 is specified for operation at a 5 m s conversion rate; with a 4 mhz input clock frequency. if the part is operated at slower clock frequencies, it may result in slightly degraded accu- racy performance from the part. this is a result of leakage ef- fects on the hold capacitor. figure 14 shows a typical plot of accuracy versus conversion time for the ad7575. conversion time C m s 2.5 5 10000 relative accuracy C lsb 50 500 2.0 1.5 1.0 0.5 0 100 1000 5000 10 t a = +25 8 c ad7575kn figure 14. accuracy vs. conversion time
ad7575 C9C rev. b unipolar operation the basic operation for the ad7575 is in the unipolar single supply mode. figure 15 shows the circuit connections to achieve this, while the nominal transfer characteristic for unipolar opera- tion is given in figure 16. since the offset and full-scale errors on the ad7575 are very small, in many cases it will not be nec- essary to adjust out these errors. if calibration is required, the procedure is as follows: offset adjust offset error adjustment in single-supply systems is easily achiev- able by means of the offset null facility of an op amp when used as a voltage follower for the analog input signal, ain. the op amp chosen should be able to operate from a single supply and allow a common-mode input voltage range that includes 0 v (e.g., tlc271). to adjust for zero offset, the input signal source is set to +4.8 mv (i.e., 1/2 lsb) while the op amp offset is varied until the adc output code flickers between 000 . . . 00 and 000 . . . 01. full-scale adjust the full scale or gain adjustment is made by forcing the analog input ain to +2.445 v (i.e., full-scale voltage C3/2 lsb). the magnitude of the reference voltage is then adjusted until the adc output code flickers between 111 . . . 10 and 111. . . 11. bipolar operation the circuit of figure 17 shows how the ad7575 can be config- ured for bipolar operation. the output code provided by the ad7575 is offset binary. the analog input voltage range is 5 v, although the voltage appearing at the ain pin of the ad7575 is in the range 0 v to +2.46 v. figure 18 shows the transfer function for bipolar operation. the lsb size is now 39.06 mv. calibration of the bipolar operation is outlined be- low. once again, because the errors are small, it may not be necessary to adjust them. to maintain specified performance without the calibration, all resistors should be 0.1% tolerance with r4 and r5 replaced by one 3.3 k w resistor and r2 and r3 replaced by one 2.5 k w resistor. offset adjust offset error adjustment is achieved by applying an analog input voltage of C4.9805 v (Cfs +1/2 lsb). resistor r3 is then adjusted until the output code flickers between 000 . . . 00 and 000 . . . 01. full-scale adjust full-scale or gain adjustment is made by applying an analog input voltage of +4.9414 v (+fs C3/2 lsb). resistor r4 is then adjusted until the output code flickers between 111 . . . 10 and 111. . . 11. a a 47 m f 0.1 m f +5v +2.46v max a a 47 m f 0.1 m f a a + C ad589 3.3k v +5v +1.23v control inputs +5v ain v ref agnd clk busy cs rd tp v dd d db7Cdb0 data out ad7575 dgnd d +5v r clk 100k v , 1% c clk 100pf, 2% figure 15. unipolar configuration output code full scale transition 11111111 11111110 11111101 00000011 00000010 00000001 00000000 fs = 2v ref 1lsb = fs 256 1lsb 3lsbs 2lsbs fs fs C1lsb ain, input voltage (in terms of lsbs) figure 16. nominal transfer characteristic for unipolar operation a a 47 m f 0.1 m f +5v a a 47 m f 0.1 m f a + C ad589 +5v +5v ain v ref clk busy cs rd tp v dd d db7Cdb0 data out ad7575 dgnd d +5v r clk 100k v , 1% c clk 100pf, 2% + a agnd r2 2.2k v r3 500 v input voltage r4 500 v r5 3k v a a +5v r7 2.5k v r6 2.5k v a tlc271 r8 3.3k v r1 10k v figure 17. bipolar configuration C1/2lsb +1/2lsb Cfs +fs C1lsb ain fs = 5v 1lsb = fs 256 output code 111...111 111...110 100...010 100...001 100...000 011...111 011...110 000...001 000...000 figure 18. nominal transfer characteristic for bipolar operation
ad7575 C10C rev. b application hints 1. noise: both the input signal lead to ain and the signal return lead from agnd should be kept as short as possible to minimize input-noise coupling. in applications where this is not possible, either a shielded cable or a twisted pair transmis- sion line between source and adc is recommended. also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. in general, the source resistance should be kept below 2 k w . larger values of source resistance can cause undesired system noise pickup. 2. proper layout: layout for a printed circuit board should ensure that digital and analog lines are kept separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. both the analog input and the reference input should be screened by agnd. a single point analog ground separate from the logic system ground, should be established at or near the ad7575. this single point analog ground subsystem should be con- nected to the digital system ground by a single-track connec- tion only. any reference bypass capacitors, analog input filter capacitors or input signal shielding should be returned to the analog ground point. ad7575 with ad589 reference the ad7575 8-bit a/d converter features a total unadjusted error specification over its entire operating temperature range. this total unadjusted error includes all errors in the a/d con- verteroffset, full scale and linearity. the one feature not pro- vided on the ad7575 is a voltage reference. this section discusses the use of the ad589 bandgap reference with the ad7575, and gives the combined reference and adc error budget over the full operating temperature range. this allows the user to compare the combined ad589/ad7575 errors to adcs whose specifications include on-chip references. two distinct application areas exist. the first is where the refer- ence voltage and the analog input voltage are derived from the same source. in other words, if the reference voltage varies, the analog input voltage range varies by a ratioed amount. in this case, the user is not worried about the absolute value of the reference voltage. the second case is where changes in the refer- ence voltage are not matched by changes in the analog input voltage range. here, the absolute value of the reference voltage, and its drift over temperature, are of prime importance. both applications are discussed below. if the analog input range varies with the reference voltage, the part is said to be operating ratiometrically. this is representative of many applications. if the reference is on-chip, and the user does not have access to it, it is not possible to get ratiometric operation. since the ad7575 uses an external reference, it can be used in ratiometric applications. however, because the part is specified with a reference of +1.23 v 5%, then the voltage range for ratiometric operation is limited. the error analysis over temperature of ratiometric applications is different from nonratiometric ones. since the reference and analog input voltage range are ratioed to each other, tempera- ture variations in the reference are matched by variations in the analog input range. therefore, the ad589 contributes no addi- tional errors over temperature to the system errors, and the combined total unadjusted error specification for the ad589 and ad7575 is as per the total unadjusted error specification in this data sheet. with nonratiometric applications, however, the analog input range stays the same if the reference varies and a full-scale error is introduced. the amount by which the reference varies deter- mines the amount of error introduced. the ad589 is graded on temperature coefficient; therefore, selection of different grades allows the user to tailor the amount of error introduced to suit the system requirements. the reference voltage from the ad589 can lie between 1.2 v and 1.25 v. this reference voltage can be adjusted for the desired full-scale voltage range using the circuit outlined in figure 19. for example, if an analog input voltage range of 0 v to +2.46 v is required, the reference should be adjusted to +1.23 v. once the reference is adjusted to the de- sired value at 25 c, the total error is as per the total unadjusted error specification on the ad7575 specification pages. (to reduce this still further, offset and full-scale errors of the ad7575 can be adjusted out using the calibration procedure outlined in this data sheet.) tlc271* +5v + C 6.8k v +5v 10k v *1k v * 10k v * ad589 *only required if it is necessary to adjust the absolute value of reference voltage. figure 19. reference adjust circuit however, it is as the temperature varies from 25 c that the ad589 starts to introduce errors. the typical temperature char- acteristics of the ad589 are shown in figure 20. the tempera- ture coefficients (tcs) represent the slopes of the diagonals of the error band from +25 c to t min and +25 c to t max . the ad589 tc is specified in ppm/ c max and is offered in four different grades.
ad7575 C11C rev. b taking the 25 c measurement as the starting point, the full-scale error introduced is always in the negative direction whether the temperature goes to t min or t max . this can be seen from the ad589 temperature characteristic shown in fig- ure 20. if the reference voltage is adjusted for 1.23 v at 45 c (for the 0 c to +70 c range) and 75 c (for the C55 c to +125 c range) the magnitude of the error introduced is reduced since it is distributed in both the positive and negative direc- tions. alternatively, this can be achieved not by adjusting at these temperatures, which would be impractical, but by adjust- ing the reference to 1.231 v instead of 1.23 v (for the extended temperature range) at 25 c. this has the required effect of distributing the plot of figure 20 more evenly about the desired value. an additional error source is the mismatch between the tem- perature coefficients (tcs) of the 10 k w and 1 k w resistors in the feedback loop of the tlc271. if these resistors have 50 ppm/ c absolute t cs, the worst case difference in drift be- tween both resistors is 100 ppm/ c. from +25 c to +125 c, this introduces a worst case shift of 1.22 mv, which results in an addi- tional full-scale error of 0.25 lsb. if 25 ppm/ c resistors are used, then the worst case error is 0.13 lsb. over the 0 c to +70 c range, the 50 ppm/ c resistors introduce an additional full-scale error of 0.11 lsb. all these errors are worst case and assume that the resistance values drift in opposite directions. in practice, resistors of the same type, and from the same manufac- turer, would drift in the same direction and hence the above error would be considerably reduced. an additional error source is the offset drift of the tlc271. this is significant only over the C55 c to +125 c range and, even in this case, it contrib- utes < 0.1 lsb worth of full-scale error. the error outlined in the right-hand column of table i is a total unadjusted error specification, excluding resistor and offset drift (the effect of these can be controlled by the user). it consists of errors from two error sources: a l lsb contribution from the ad7575 (including full-scale, offset and relative accuracy er- rors), and the remainder is a full-scale error introduced by the ad589. it is important to note that the variation of the ad589 voltage only introduces a full-scale error; the relative accuracy (or endpoint nonlinearity) of the system, with a top grade ad7575, is still 1/2 lsb (i.e., 8-bits accurate). temperature C 8 c 1.2370 1.2365 1.2345 C50 125 C25 output voltage C v 0 255075100 1.2360 1.2355 1.2350 figure 20. typical ad589 temperature characteristics the effect the tc has on the system error is that it introduces a full-scale error in the adc. this, in turn, affects the total unad- justed error specification. for example, using the ad589kh with a 50 ppm/ c max tc the change in reference voltage from 25 c to 70 c will be from 1.23 v to 1.22724 v, a change of C 2.76 mv. this results in a change in the full-scale range of the adc of C5.52 mv, since the full-scale range on the ad7575 is 2 v ref . because the lsb size for the ad7575 is 9.61 mv, the ad589 introduces an additional full-scale error of C0.57 lsbs on top of the existing full-scale error specification for the adc. since the total unadjusted error specification for the adc includes the full-scale error, there is also a corresponding in- crease in the total unadjusted error of C0.57 lsbs. the change in reference voltage at 0 c is C1.5 mv, resulting in a full-scale change of C3 mv or C0.31 lsbs worth of ful l-scale error. table i shows the amount of additional total unadjusted error, which is introduced by the temperature variation of the ad589, for different grades and for different temperature ranges. this table applies only to nonratiometric applications, because the tem- perature variation of the reference does not affect the system error in ratiometric applications as outlined earlier. it shows the amount of error introduced over t min to t max for a system in which the reference has been adjusted to the desired value at 25 c. the final or right-most column of the table gives the total combined error for the ad589 and the top grade ad7575. table i. ad589/ad7575 error over temperature (nonratiometric applications) full-scale error introduced combined worst case ad589 temperature by ad589 @ t max ad589/ad7575 grade range (worst case) t.u.e. @ t max ad589jh 0 c to +70 c C1.15 lsb C2.15 lsb ad589kh 0 c to +70 c C0.57 lsb C1.57 lsb ad589lh 0 c to +70 c C0.29 lsb C1.29 lsb ad589mh 0 c to +70 c C0.115 lsb C1.115 lsb ad589sh C55 c to +125 c C2.56 lsb C3.56 lsb ad589th C55 c to +125 c C1.28 lsb C2.28 lsb ad589uh C55 c to +125 c C0.64 lsb C1.64 lsb *excluding resistor and offset drift.
ad7575 C12C rev. b c945bC0C7/98 printed in u.s.a. 20-terminal lccc (e-20a) 1 20 4 9 8 13 19 bottom view 14 3 18 0.082 6 0.018 (2.085 6 0.455) 0.350 6 0.008 (8.89 6 0.20) sq 0.020 3 45 8 (0.51 3 45 8 ) ref 0.040 3 45 8 (1.02 3 45 8 ) ref 3 plcs 0.025 6 0.003 (0.635 6 0.075) 0.050 (1.27) outline dimensions dimensions shown in inches and (mm). 18-lead plastic dip (n-18) 18 19 10 0.91 (23.12) 0.89 (22.61) 0.26 (6.61) 0.24 (6.10) pin 1 seating plane 0.105 (2.67) 0.095 (2.42) 0.02 (0.508) 0.015 (0.381) 0.18 (4.58) max 0.065 (1.66) 0.045 (1.15) 0.175 (4.45) 0.12 (3.05) 0.306 (7.78) 0.294 (7.47) 0.12 (0.305) 0.008 (0.203) 0.14 (3.56) 0.12 (3.05) 15 8 0 20-lead plcc (p-20a) 3 pin 1 identifier 4 19 18 8 9 14 13 top view (pins down) sq 0.390 6 0.005 (9.905 6 0.125) sq 0.353 6 0.003 (8.966 6 0.076) 0.020 (0.51) max 0.050 (1.27) 0.045 6 0.003 (1.143 6 0.076) 0.029 6 0.003 (0.737 6 0.076) 0.017 6 0.004 (0.432 6 0.101) 0.020 (0.51) min 0.025 (0.64) min 0.105 6 0.015 (2.665 6 0.375) 0.173 6 0.008 (4.388 6 0.185) 0.035 6 0.01 (0.89 6 0.25) r 18-lead cerdip (q-18) 18 1 9 10 0.310 (7.874) 0.260 (6.604) pin 1 seating plane 0.023 (0.584) 0.015 (0.381) 0.950 (24.13) max 0.070 (1.778) 0.030 (0.762) 0.200 (5.080) 0.125 (3.175) 0.060 (1.524) 0.015 (0.381) 0.180 (4.572) 0.140 (3.556) 0.110 (2.794) 0.090 (2.286) 0.320 (8.128) 0.290 (7.366) 0.015 (0.381) 0.008 (0.203) 0.400 (10.160) 0.330 (8.382) 18-lead soic (r-18) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc
package/price information cmos, 5 s 8 - bit sampling adc * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. model status package description pin count temperature range price* (100 - 499) 5962 - 8776202vx production cerdip glass seal 18 military $43.56 ad7575aq production cerdip glass seal 18 industrial $7.70 ad7575bchips pre - release chips/die sales 18 commercial - ad7575bq production cerdip glass seal 18 industrial - ad7575jn production plastic/epoxy dip 18 commercial $5.50 ad7575jp pre-release plastic lead chip carrier 20 commercial $6.30 ad7575jp-reel production plastic lead chip carrier 20 commercial - ad7575jr production std s.o. pkg (soic) 18 commercial $5.50 ad7575kn production plastic/epoxy dip 18 commercial - ad7575kp production plastic lead chip carrier 20 commercial - ad7575kp-reel production plastic lead chip carrier 20 commercial -

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